By Kanupriya Gulati
Single-threaded software program functions have ceased to determine signi?cant earnings in p- formance on a general-purpose CPU, regardless of extra scaling in very huge scale integration (VLSI) know-how. it is a signi?cant challenge for digital layout automation (EDA) purposes, because the layout complexity of VLSI built-in circuits (ICs) is continually transforming into. during this learn monograph, we assessment customized ICs, ?eld-programmable gate arrays (FPGAs), and pictures processors as structures for accelerating EDA algorithms, rather than the general-purpose sing- threaded CPU. We examine purposes that are utilized in key time-consuming steps of the VLSI layout ?ow. additional, those functions even have various levels of inherent parallelism in them. We research either control-dominated EDA purposes and regulate plus information parallel EDA functions. We speed up those functions on those diversified systems. We additionally current an automatic process for accelerating definite uniprocessor functions on a portraits processor. This monograph compares customized ICs, FPGAs, and pictures processing devices (GPUs) as capability structures to speed up EDA algorithms. It additionally offers information of the programming version used for interfacing with the GPUs.
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Extra resources for Hardware Acceleration of EDA Algorithms: Custom ICs, FPGAs and GPUs
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