Hardware Acceleration of EDA Algorithms: Custom ICs, FPGAs and GPUs

By Kanupriya Gulati

Single-threaded software program functions have ceased to determine signi?cant earnings in p- formance on a general-purpose CPU, regardless of extra scaling in very huge scale integration (VLSI) know-how. it is a signi?cant challenge for digital layout automation (EDA) purposes, because the layout complexity of VLSI built-in circuits (ICs) is continually transforming into. during this learn monograph, we assessment customized ICs, ?eld-programmable gate arrays (FPGAs), and pictures processors as structures for accelerating EDA algorithms, rather than the general-purpose sing- threaded CPU. We examine purposes that are utilized in key time-consuming steps of the VLSI layout ?ow. additional, those functions even have various levels of inherent parallelism in them. We research either control-dominated EDA purposes and regulate plus information parallel EDA functions. We speed up those functions on those diversified systems. We additionally current an automatic process for accelerating definite uniprocessor functions on a portraits processor. This monograph compares customized ICs, FPGAs, and pictures processing devices (GPUs) as capability structures to speed up EDA algorithms. It additionally offers information of the programming version used for interfacing with the GPUs.

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References 1. advertisement fault simulation instrument. Licensing contract with the software seller calls for that we don't expose the identify of the device or its seller. 2. IWLS 2005 Benchmarks. http://www. iwls. org/iwls2005/benchmarks. html three. NVIDIA Tesla GPU Computing Processor. http://www. nvidia. com/object/IO_ 43499. html four. Abramovici, A. , Levendel, Y. , Menon, P. : A good judgment simulation engine. In: IEEE Transactions on Computer-Aided layout, vol. 2, pp. 82–94 (1983) five. Agrawal, P. , Dally, W. J. , Fischer, W. C. , Jagadish, H. V. , Krishnakumar, A. S. , Tutundjian, R. : MARS: A multiprocessor-based programmable accelerator. IEEE layout and try four (5), 28– 36 (1987) 6. Amin, M. B. , Vinnakota, B. : Workload distribution in fault simulation. magazine of digital checking out 10(3), 277–282 (1997) 7. Amin, M. B. , Vinnakota, B. : facts parallel fault simulation. IEEE Transactions on Very huge Scale Integration (VLSI) platforms 7(2), 183–190 (1999) eight. Banerjee, P. : Parallel Algorithms for VLSI Computer-aided layout. Prentice corridor Englewood Cliffs, NJ (1994) nine. Beece, D. ok. , Deibert, G. , Papp, G. , Villante, F. : The IBM engineering verification engine. In: DAC ’88: complaints of the twenty fifth ACM/IEEE convention on layout Automation, pp. 218–224. IEEE desktop Society Press, Los Alamitos, CA (1988) 10. Gulati, ok. , Khatri, S. P. : in the direction of acceleration of fault simulation utilizing images processing devices. In: complaints, IEEE/ACM layout Automation convention (DAC), pp. 822–827 (2008) 132 eight Accelerating Fault Simulation utilizing pictures Processors eleven. Ishiura, N. , Ito, M. , Yajima, S. : High-speed fault simulation utilizing a vector processor. In: court cases of the foreign convention on Computer-Aided layout (ICCAD) (1987) 12. Mueller-Thuns, R. , Saab, D. , Damiano, R. , Abraham, J. : VLSI good judgment and fault simulation on general-purpose parallel desktops. In: IEEE Transactions on Computer-Aided layout of built-in Circuits and platforms, vol. 12, pp. 446–460 (1993) thirteen. Narayanan, V. , Pitchumani, V. : Fault simulation on vastly parallel simd machines: Algorithms, implementations and effects. magazine of digital trying out 3(1), 79–92 (1992) 14. Ozguner, F. , Aykanat, C. , Khalid, O. : good judgment fault simulation on a vector hypercube multiprocessor. In: lawsuits of the 3rd convention on Hypercube concurrent pcs and functions, pp. 1108–1116 (1988) 15. Ozguner, F. , Daoud, R. : Vectorized fault simulation at the Cray X-MP supercomputer. In: Computer-Aided layout, 1988. ICCAD-88. Digest of Technical Papers, IEEE overseas convention on, pp. 198–201 (1988) sixteen. Parkes, S. , Banerjee, P. , Patel, J. : A parallel set of rules for fault simulation in line with PROOFS. pp. 616–621. URL citeseer. ist. psu. edu/article/ parkes95parallel. html 17. Patil, S. , Banerjee, P. : functionality trade-offs in a parallel try generation/fault simulation setting. In: IEEE Transactions on Computer-Aided layout, pp. 1542–1558 (1991) 18. Pfister, G. F. : The Yorktown simulation engine: advent. In: DAC ’82: lawsuits of the nineteenth convention on layout Automation, pp. 51–54. IEEE Press, Piscataway, NJ (1982) 19.

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